Capacitive sensing technology can detect the proximity of objects from one another. For example, capacitive sensing technology is often used to detect a human body part (e.g., finger) position on a touch input device by measuring the capacitive coupling between the human finger and a capacitive sensor (e.g., touchscreen).
In some conventional capacitive sensing systems, a form of delta-sigma modulation can be used, with successive changes in the input signal over time being encoded into values. This is in contrast to other conventional approaches that can measure an actual value of the input signal. In the delta-sigma case, typically each encoded value can be a stream of bits, which can be integrated to provide a representation of the input signal.
A conventional sigma-delta capacitance sensing system 1800 is shown in FIG. 18A. Conventional system 1800 can sense changes in capacitance at a sense node 1801. Conventional system 1800 can include a current source 1803, a modulating switch 1805, a comparator 1807, logic 1809, a timer/counter 1811, and a sampling switch 1813. A modulating capacitance Cmod can be connected to sense node 1801 to provide a base capacitance. A variable capacitance for detection is shown as Cs.
FIG. 18B is a timing diagram showing an operation of system 1800. FIG. 18B includes a waveforms showing a sampling timer signal (Timer), a voltage at sense node 1801 (VCmod), an output of comparator 1807 (Comp Output), a counter value provided by timer/counter 1811 (Counter), and an integrating clock signal CLK.
Operations of a conventional system 1800 will now be described with reference to FIG. 18A in conjunction with FIG. 18B.
In the conventional approach shown in FIG. 18B, a sampling operation can involve a number of conversion cycles, each of which represents an integration of the capacitance at the sense node 1801 to generate a count value. Such count values are accumulated to generate a sample value.
At time t0, a Timer signal can go high, signaling the start of a sample operation and the start of a first conversion cycle. Sample switch 1813 can switch from a grounded position to one that connects a sampled capacitance Cs to sense node 1801. In the operation shown, VCmod is compared to a reference voltage Vref by comparator 1807. Because VCmod was previously grounded, it is less than Vref, and Comp Output is high. This enables modulating switch 1805, which causes current source 1803 to charge the sense node 1801. Logic 1809 outputs the high Comp Output value to time/counter 1811, which can increment a count value according to CLK.
At about time t1, VCmod can reach Vref. Consequently, comparator 1807 can drive Comp Output low. This disables modulating switch 1805, which isolates current source 1803 from sense node 1801, to stop the charging of sense node 1801. Logic 1809 latches the low Comp Output value, and forwards it to timer/counter 1811, which ceases incrementing its count. In the example shown, the count value is 8 (cycles of CLK).
At about time t2, a first conversion cycle can end. At this time, sample switch 1813 can discharge the sampled capacitance Cs to ground. A sense node 1801 may also be discharged to ground. As shown, a conventional conversion cycle can be from 0.2 to 10 us.
At time t3, a second conversion cycle starts and proceeds as described for the first conversion cycle. However, in the second conversion cycle the accumulated count is 11, for an overall counter value of 19.
At time t4, a last conversion cycle is complete, with the Timer signal going low. As shown, the total sample raw count is 3504, which represents a total of the integrations performed at the sense node 1801 over all the conversion cycles of the sample operation. Sequences of raw sample counts derived in this manner can indicate any changes in Cs.
A drawback to a conventional approach, like that of FIGS. 18A and 18B, can be the sensitivity of the system to variations in reference levels and timing clocks. In particular, a sensitivity of a conventional capacitive sensing system like that of FIG. 18A can be given bySensitivity=(ΔRC/ΔCs)=(Vref*Fs/Idac)*(2n−1)where ΔRC is the raw count provided by a variation of ΔCs in the sample capacitance. Fs can be the frequency of integrating clock signal CLK, Idac is the current provided by current source 1803, and n is the number of samples.
From the above, it can be seen that any short term variation (e.g., noise) in Vref or Fs translates into a proportional ΔRC error. In order to sense a 0.1% ΔCs sense capacitance variation, Vref and Fs are required to vary less than 0.01% for the duration of the measurement cycle. As a result, conventional approaches can employ low noise reference generators to ensure strict Vref values, as well as low jitter, high stability oscillators to ensure CLK is maintained as close as possible to a desired Fs.
Conventional approaches can also have conversion transfer functions that vary considerably from an ideal conversion result. In particular, a conventional transfer function can have “flat” regions, instead of a linear response. To address such flat regions, conventional approaches can utilize clock dithering, which requires additional circuits to alter the sampling clock. Further, due to the high dependence upon an accurate reference voltage, conventional approaches can require periodic recalibration.
It is noted that the conventional circuit 1800 can be considered not to be a “true” sigma-delta converter, as its output depends upon the clock frequency (i.e., Fs).